(1) Field of the Invention
The present invention relates to a semiconductor device, and more specifically to a semiconductor memory device of a so-called one-transistor-type having a capacitor element per one memory unit, and a field effect transistor which is connected in series with the capacitor element.
(2) Description of the Prior Art
The one-transistor-type dynamic memory has hitherto usually been developed in such a manner that an MOS field effect transistor serves as a switching transistor. A representative dynamic memory of this type consists of an MOS transistor and an MOS capacitor which is disposed on an extension of the drain electrode (or source electrode) of the MOS transistor. The MOS capacitor consists of a polycrystalline silicon layer which serves as one electrode, an inversion layer which is formed on the surface of a silicon semiconductor substrate and which serves as another electrode, and a dielectric film which is interposed therebetween. On the other hand, the source electrode (or drain electrode) of the MOS transistor is connected to a bit line, the gate electrode is connected to a word line, and another electrode of the MOS capacitor is connected to a constant potential supply.
The data storing mechanism of the memory cell of the above-mentioned construction works based upon the presence or absence of the electric charge accumulated in the MOS capacitor element. By detecting the presence or absence of the electric charge, the stored data can be taken to the external units. Therefore, the capacitor element should be capable of storing as much electric charge as possible, the electric charge should be detected as effectively as possible when the data is to be read, and the parasitic capacity of the bit lines should be kept as small as possible.
The output voltage applied to the bit line, however, decreases with the increase in the degree of memory integration and with the increase in the number of cells per bit line. To prevent this inconvenience, therefore, attempts having been made to decrease the parasitic capacity of the bit lines and to increase the areas of the MOS capacitor. For example, it has been known that the parasitic capacity relative to ground decreases, and the output voltage of the cell increases, if the bit lines are formed by using a metal layer, instead of relying upon high impurity concentration regions which form the source and drain electrodes of the MOS transistor. It has also been attempted to stack the capacitors and MOS transistors in a three-dimensional manner to increase the storage capacity of a memory cell which has a limited area. The cells produced by this method are usually called stack-type cells. According to this method, the reduction in the cell area enables the bit line to be shortened and, eventually, the parasitic capacity to be reduced.
The defect of the stack-type cell is that a bit line must be wired over a portion having a large step which results from the multi-layer structure. As the distance between the neighboring cells is reduced, the inclination of the bit line becomes steep; and the bit line tends to be easily broken. Therefore, even if it is attempted to reduce the areas of unit cells of a multi-layer construction, space must be provided among the neighboring cells to such a degree that the wiring will not break. Therefore, a limitation is imposed on the degree of integration.